Freescale Semiconductor /SKEAZN642 /ICS /C1

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Interpret as C1

7 43 0 0 00 0 0 0 0 0 0 0 0 (0)IREFSTEN 0 (0)IRCLKEN 0 (0)IREFS 0RDIV0 (00)CLKS

IREFS=0, CLKS=00, IRCLKEN=0, IREFSTEN=0

Description

ICS Control Register 1

Fields

IREFSTEN

Internal Reference Stop Enable

0 (0): Internal reference clock is disabled in Stop mode.

1 (1): Internal reference clock stays enabled in Stop mode if IRCLKEN is set, or if ICS is in FEI, FBI, or FBILP mode before entering Stop.

IRCLKEN

Internal Reference Clock Enable

0 (0): ICSIRCLK is inactive.

1 (1): ICSIRCLK is active.

IREFS

Internal Reference Select

0 (0): External reference clock is selected.

1 (1): Internal reference clock is selected.

RDIV

Reference Divider

CLKS

Clock Source Select

0 (00): Output of FLL is selected.

1 (01): Internal reference clock is selected.

2 (10): External reference clock is selected.

3 (11): Reserved, defaults to 00.

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